AD698 LVDTs connected in the series opposed configuration. Both ex- Application Circuit

Analog Devices, Inc.

find AD698 datasheet
AD698 circuit
AD698
CONNECTING THE AD698
The AD698 can easily be connected for dual or Single Supply
operation as shown in Figures 7, 8 and 13. The following gen-
eral design procedures demonstrate how external component
values are selected and can be used for any LVDT that meets
AD698 input/output criteria. The connections for the A and B
channels and the A channel Comparators will depend on which
transducer is used. In general follow the guidelines below.
Parameters set with external passive components include: exci-
tation frequency and amplitude, AD698 input signal frequency,
and the scale factor (V/inch). Additionally, there are optional
features; offset null adjustment, filtering, and signal integration,
which can be implemented by adding external components.
+15V
–15V
6.8µF
100nF
1 –V
S
2 EXC1
3 EXC2
4 LEV1
R1
5 LEV2
C1
15nF
SIG OUT 20
R2
33kΩ
C4
7 FREQ2
8 BFILT1
C2
9 BFILT2
10 –BIN
11 +BIN
12 –AIN
AFILT2 16
–ACOMP 15
+ACOMP 14
+AIN 13
OUT FILT 18
AFILT1 17
C3
1000pF
V
OUT
6.8µF
100nF
3. Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. The Schaevitz E100 for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.
4. Select excitation frequency determining component C1.
C1
=
35
µF
Hz/f
EXCITATION
+15V
–15V
6.8µF
100nF
1 –V
S
2 EXC1
3 EXC2
4 LEV1
R1
5 LEV2
SIG OUT 20
R2
6.8µF
100nF
AD698
+V
S
24
R4
R3
OFFSET1 23
OFFSET2 22
SIG REF 21
R
L
V
OUT
SIGNAL
REFERENCE
AD698
+V
S
24
R4
R3
C1
6 FREQ1 FEEDBACK 19
C4 1000pF
7 FREQ2
OUT FILT 18
AFILT1 17
C3
9 BFILT2
10 –BIN
11 +BIN
12 –AIN
AFILT2 16
–ACOMP 15
+ACOMP 14
A
+AIN 13
PHASE
LAG/LEAD
NETWORK
C
D
B
OFFSET1 23
OFFSET2 22
SIG REF 21
R
L
SIGNAL
REFERENCE
8 BFILT1
C2
6 FREQ1 FEEDBACK 19
1M
PHASE LAG
A
B
C
R
T
C
D
PHASE LEAD
A
B
R
T
R
S
C
D
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R
S
// (R
S
+ R
T
)
R
S
R
S
C
C
Figure 7. Interconnection Diagram for Half-Bridge LVDT
and Dual Supply Operation
DESIGN PROCEDURE
DUAL SUPPLY OPERATION
Figure 8. AD698 Interconnection Diagram for Series
Opposed LVDT and Dual Supply Operation
B. Determine the Oscillator Amplitude
Figure 7 shows the connection method for half-bridge LVDTs.
Figure 8 demonstrates the connections for 3- and 4-WIRE
LVDTs connected in the series opposed configuration. Both ex-
amples use dual
±
15 volt power supplies.
A. Determine the Oscillator Frequency
Frequency is often determined by the required BW of the sys-
tem. However, in some systems the frequency is set to match
the LVDT zero phase frequency as recommended by the
manufacturer; in this case skip to Step 4.
1. Determine the mechanical bandwidth required for LVDT
position measurement subsystem, f
SUBSYSTEM
. For this ex-
ample, assume f
SUBSYSTEM
= 250 Hz.
2. Select minimum LVDT excitation frequency approximately
10
×
f
SUBSYSTEM
. Therefore, let excitation frequency = 2.5 kHz.
Amplitude is set such that the primary signal is in the 1.0 V to
3.5 V rms range and the secondary signal is in the 0.25 V to
3.5 V rms range when the LVDT is at its mechanical full-scale
position. This optimizes linearity and minimizes noise suscepti-
bility. Since the part is ratiometric, the exact value of the excita-
tion is relatively unimportant.
5. Determine optimum LVDT excitation voltage, V
EXC
. For a
4-WIRE LVDT determine the voltage transformation ratio,
VTR, of the LVDT at its mechanical full scale. VTR =
LVDT sensitivity
×
Maximum Stroke Length from null.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of volts output per volts input per inch dis-
placement. The E100 has a sensitivity of 2.4 mV/V/mil. In
the event that LVDT sensitivity is not given by the manufac-
turer, it can be computed. See section on determining LVDT
sensitivity.
–6–
REV. B