Fds8928a Dual N & P-channel Enhancement Mode Field Effect Transistor

Part No :
FDS8928A pinout
File Size : 19 KB
Pages : 9 Pages

Other Part Numbers in this pdf file

Fairchild Semiconductor

find FDS8928A datasheet
FDS8928A pinout,FDS8928A pin diagram
July 1998
FDS8928A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P -Channel enhancement mode power
field effect Transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other Battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
Features
N-Channel 5.5 A,30 V, R
DS(ON)
=0.030
@ V
GS
=4.5 V
R
DS(ON)
=0.038
@ V
GS
=2.5 V.
P-Channel -4 A,-20 V, R
DS(ON)
=0.055
@ V
GS
=-4.5 V
R
DS(ON)
=0.072
@ V
GS
=-2.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
SuperSOT
TM
-6
SuperSOT -8
TM
SO-8
SOIC-16
D2
D1
D1
D2
5
6
7
4
3
2
1
DS A
F 8
2
89
S2
G2
G1
8
SO-8
pin
1
S1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
P
D
T
A
= 25°C unless otherwise noted
N-Channel
30
8
(Note 1a)
P-Channel
-20
-8
-4
-20
2
Units
V
V
A
5.5
20
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
1.6
1
0.9
-55 to 150
°C
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
θJA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDS8928A Rev. B