Precision Timers

  /ORDERING INFORMATION These devices NA555 NE555 SA555 SE555 are precision timing Circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external Resistor and Capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external Resistors and a single external Capacitor The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the Flip-Flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the Flip-Flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the Flip-Flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
Item: NE555P
File Size : 72 KB
Pages : 27 Pages

Other Part Numbers in this pdf file

SE555P   SE555N   SE555JGB   SE555JG   SE555FKB   SE555DRG4   SE555DR   SE555DG4   SE555D   SE555   SA555PE4   SA555P   SA555DRG4   SA555DRE4   SA555DR   SA555DG4   SA555DE4   SA555D   NE555Y   NE555PWRG4  
Texas Instruments Incorporated
Draw NE555P Schematic Online for Free

Related Datasheets

NE555P Related Keywords:

NE555P Cross Reference NE555P Schematic NE555P Equivalent NE555P RoHS
NE555P Application Notes NE555P Circuits NE555P Pinout NE555P PDF
NE555P 数据手册 NE555P 电路 NE555P 引脚 NE555P Download